1. Technical Field
The present invention relates to a shared MAC (Multiply Accumulate) system and a method therefor, and in particular to a method whereby a MAC unit of a sub-processor is employed in common by the sub-processor and a host processor.
2. Prior Art
For a low end application, an integrated dual processor module that provides a high performance at low cost has been proposed for which a host processor and a sub-processor are integrated in a single chip and are independently operated. A host processor can be, for example, a CISC microcontroller for controlling the entire apparatus, and a sub-processor can be, for example, a fuzzy processor for performing a DSP function.
FIG. 1 is a block diagram illustrating the arrangement of a conventional integrated dual processor module. A CISC host processor 1 and a sub-processor 2 are connected by a host bus interface 3. In the sub-processor 2 are provided a memory 4 and a multiply accumulate (MAC) unit 5, which performs the important function required of the sub-processor 2. The MAC unit 5 of the sub-processor 2 normally performs a routine process, such as servo control for which repetitious MAC operations are required, while the microprocessor 1 is primarily responsible for overall system control. The exchange of data by means of interrupt signals transmitted via a memory or a register that is used in common has been proposed as a method by which the two processors can communicate.
In the conventional system, if a single MAC operation must be performed in a processing sequence handled by the host processor 1, either a multiplication instruction and an addition instruction provided for the host processor 1 must be combined to perform the MAC operation, or interrupt processing must be performed to assign the execution of the MAC operation to the MAC unit 5 in the sub-processor 2. In either case, however, a relatively long execution time is required for the processing. Particularly in the latter case, where the host processor 1 employs the interrupt process to assign the MAC operation to the sub-processor 2, the time required for the interrupt processing constitutes a bottleneck for its execution. Therefore, there is a demand for the development of a more efficient system whereby the MAC unit 5 in the sub-processor 2 can be employed in common by the sub-processor 2 and the host processor 1 without any interrupt processing being required.
It is one object of the present invention to improve the operational performance of an integrated dual processor module by reducing the period of time required for the processing performed by a host processor.
It is another object of the present invention to provide an efficient system whereby a Multiply Accumulate (MAC) unit in a sub-processor can be employed in common by the sub-processor and a host processor.